`ifndef _ral_blk_PPU_REG_ppu_reg_rtl_
`define _ral_blk_PPU_REG_ppu_reg_rtl_

`include "vmm_ral_host_itf.sv"

`include "ral_reg_PPU_REG_ppu_reg_PORT_SEL_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_MODE_SEL_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_SPT_HEAD_ERR_CNT_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_SPT_TAIL_ERR_CNT_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_SPT_SHT_PKT_CNT_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_SPT_LNG_PKT_CNT_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_SPT_OK_PKT_CNT_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA0_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA1_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA2_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA3_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA4_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA5_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA6_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA7_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA8_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA9_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA10_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA11_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA12_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA13_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA14_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_DATA15_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_STATUS_rtl.sv"
`include "ral_reg_PPU_REG_ppu_reg_TEST_ALARM_rtl.sv"


interface ral_blk_PPU_REG_ppu_reg_itf();

logic [0:0] port_sel_out;
logic port_sel_rd, port_sel_wr;
logic port_sel_wen;
logic [0:0] port_sel_in;

logic [7:0] mode_sel_out;
logic mode_sel_rd, mode_sel_wr;
logic mode_sel_wen;
logic [7:0] mode_sel_in;

logic [31:0] head_err_cnt_out;
logic head_err_cnt_rd, head_err_cnt_wr;
logic [31:0] head_err_cnt_in;
logic head_err_cnt_wen;

logic [31:0] tail_err_cnt_out;
logic tail_err_cnt_rd, tail_err_cnt_wr;
logic [31:0] tail_err_cnt_in;
logic tail_err_cnt_wen;

logic [31:0] short_pkt_cnt_out;
logic short_pkt_cnt_rd, short_pkt_cnt_wr;
logic [31:0] short_pkt_cnt_in;
logic short_pkt_cnt_wen;

logic [31:0] long_pkt_cnt_out;
logic long_pkt_cnt_rd, long_pkt_cnt_wr;
logic [31:0] long_pkt_cnt_in;
logic long_pkt_cnt_wen;

logic [31:0] ok_pkt_cnt_out;
logic ok_pkt_cnt_rd, ok_pkt_cnt_wr;
logic [31:0] ok_pkt_cnt_in;
logic ok_pkt_cnt_wen;

logic [23:0] TEST_DATA0_data_out;
logic TEST_DATA0_data_rd, TEST_DATA0_data_wr;
logic TEST_DATA0_data_wen;
logic [23:0] TEST_DATA0_data_in;

logic [23:0] TEST_DATA1_data_out;
logic TEST_DATA1_data_rd, TEST_DATA1_data_wr;
logic TEST_DATA1_data_wen;
logic [23:0] TEST_DATA1_data_in;

logic [23:0] TEST_DATA2_data_out;
logic TEST_DATA2_data_rd, TEST_DATA2_data_wr;
logic TEST_DATA2_data_wen;
logic [23:0] TEST_DATA2_data_in;

logic [23:0] TEST_DATA3_data_out;
logic TEST_DATA3_data_rd, TEST_DATA3_data_wr;
logic TEST_DATA3_data_wen;
logic [23:0] TEST_DATA3_data_in;

logic [23:0] TEST_DATA4_data_out;
logic TEST_DATA4_data_rd, TEST_DATA4_data_wr;
logic TEST_DATA4_data_wen;
logic [23:0] TEST_DATA4_data_in;

logic [23:0] TEST_DATA5_data_out;
logic TEST_DATA5_data_rd, TEST_DATA5_data_wr;
logic TEST_DATA5_data_wen;
logic [23:0] TEST_DATA5_data_in;

logic [23:0] TEST_DATA6_data_out;
logic TEST_DATA6_data_rd, TEST_DATA6_data_wr;
logic TEST_DATA6_data_wen;
logic [23:0] TEST_DATA6_data_in;

logic [23:0] TEST_DATA7_data_out;
logic TEST_DATA7_data_rd, TEST_DATA7_data_wr;
logic TEST_DATA7_data_wen;
logic [23:0] TEST_DATA7_data_in;

logic [23:0] TEST_DATA8_data_out;
logic TEST_DATA8_data_rd, TEST_DATA8_data_wr;
logic TEST_DATA8_data_wen;
logic [23:0] TEST_DATA8_data_in;

logic [23:0] TEST_DATA9_data_out;
logic TEST_DATA9_data_rd, TEST_DATA9_data_wr;
logic TEST_DATA9_data_wen;
logic [23:0] TEST_DATA9_data_in;

logic [23:0] TEST_DATA10_data_out;
logic TEST_DATA10_data_rd, TEST_DATA10_data_wr;
logic TEST_DATA10_data_wen;
logic [23:0] TEST_DATA10_data_in;

logic [23:0] TEST_DATA11_data_out;
logic TEST_DATA11_data_rd, TEST_DATA11_data_wr;
logic TEST_DATA11_data_wen;
logic [23:0] TEST_DATA11_data_in;

logic [23:0] TEST_DATA12_data_out;
logic TEST_DATA12_data_rd, TEST_DATA12_data_wr;
logic TEST_DATA12_data_wen;
logic [23:0] TEST_DATA12_data_in;

logic [23:0] TEST_DATA13_data_out;
logic TEST_DATA13_data_rd, TEST_DATA13_data_wr;
logic TEST_DATA13_data_wen;
logic [23:0] TEST_DATA13_data_in;

logic [23:0] TEST_DATA14_data_out;
logic TEST_DATA14_data_rd, TEST_DATA14_data_wr;
logic TEST_DATA14_data_wen;
logic [23:0] TEST_DATA14_data_in;

logic [23:0] TEST_DATA15_data_out;
logic TEST_DATA15_data_rd, TEST_DATA15_data_wr;
logic TEST_DATA15_data_wen;
logic [23:0] TEST_DATA15_data_in;

logic [1:0] status_a_in;
logic status_a_rd;
logic [1:0] status_b_in;
logic status_b_rd;

logic [0:0] data_err_a_in;
logic data_err_a_rd;
logic [0:0] addr_err_a_in;
logic addr_err_a_rd;
logic [0:0] data_err_b_in;
logic data_err_b_rd;
logic [0:0] addr_err_b_in;
logic addr_err_b_rd;


modport regs(output port_sel_out,
             output port_sel_rd,
             output port_sel_wr,
             input port_sel_wen,
             input port_sel_in,
             output mode_sel_out,
             output mode_sel_rd,
             output mode_sel_wr,
             input mode_sel_wen,
             input mode_sel_in,
             output head_err_cnt_out,
             output head_err_cnt_rd,
             output head_err_cnt_wr,
             input head_err_cnt_in,
             input head_err_cnt_wen,
             output tail_err_cnt_out,
             output tail_err_cnt_rd,
             output tail_err_cnt_wr,
             input tail_err_cnt_in,
             input tail_err_cnt_wen,
             output short_pkt_cnt_out,
             output short_pkt_cnt_rd,
             output short_pkt_cnt_wr,
             input short_pkt_cnt_in,
             input short_pkt_cnt_wen,
             output long_pkt_cnt_out,
             output long_pkt_cnt_rd,
             output long_pkt_cnt_wr,
             input long_pkt_cnt_in,
             input long_pkt_cnt_wen,
             output ok_pkt_cnt_out,
             output ok_pkt_cnt_rd,
             output ok_pkt_cnt_wr,
             input ok_pkt_cnt_in,
             input ok_pkt_cnt_wen,
             output TEST_DATA0_data_out,
             output TEST_DATA0_data_rd,
             output TEST_DATA0_data_wr,
             input TEST_DATA0_data_wen,
             input TEST_DATA0_data_in,
             output TEST_DATA1_data_out,
             output TEST_DATA1_data_rd,
             output TEST_DATA1_data_wr,
             input TEST_DATA1_data_wen,
             input TEST_DATA1_data_in,
             output TEST_DATA2_data_out,
             output TEST_DATA2_data_rd,
             output TEST_DATA2_data_wr,
             input TEST_DATA2_data_wen,
             input TEST_DATA2_data_in,
             output TEST_DATA3_data_out,
             output TEST_DATA3_data_rd,
             output TEST_DATA3_data_wr,
             input TEST_DATA3_data_wen,
             input TEST_DATA3_data_in,
             output TEST_DATA4_data_out,
             output TEST_DATA4_data_rd,
             output TEST_DATA4_data_wr,
             input TEST_DATA4_data_wen,
             input TEST_DATA4_data_in,
             output TEST_DATA5_data_out,
             output TEST_DATA5_data_rd,
             output TEST_DATA5_data_wr,
             input TEST_DATA5_data_wen,
             input TEST_DATA5_data_in,
             output TEST_DATA6_data_out,
             output TEST_DATA6_data_rd,
             output TEST_DATA6_data_wr,
             input TEST_DATA6_data_wen,
             input TEST_DATA6_data_in,
             output TEST_DATA7_data_out,
             output TEST_DATA7_data_rd,
             output TEST_DATA7_data_wr,
             input TEST_DATA7_data_wen,
             input TEST_DATA7_data_in,
             output TEST_DATA8_data_out,
             output TEST_DATA8_data_rd,
             output TEST_DATA8_data_wr,
             input TEST_DATA8_data_wen,
             input TEST_DATA8_data_in,
             output TEST_DATA9_data_out,
             output TEST_DATA9_data_rd,
             output TEST_DATA9_data_wr,
             input TEST_DATA9_data_wen,
             input TEST_DATA9_data_in,
             output TEST_DATA10_data_out,
             output TEST_DATA10_data_rd,
             output TEST_DATA10_data_wr,
             input TEST_DATA10_data_wen,
             input TEST_DATA10_data_in,
             output TEST_DATA11_data_out,
             output TEST_DATA11_data_rd,
             output TEST_DATA11_data_wr,
             input TEST_DATA11_data_wen,
             input TEST_DATA11_data_in,
             output TEST_DATA12_data_out,
             output TEST_DATA12_data_rd,
             output TEST_DATA12_data_wr,
             input TEST_DATA12_data_wen,
             input TEST_DATA12_data_in,
             output TEST_DATA13_data_out,
             output TEST_DATA13_data_rd,
             output TEST_DATA13_data_wr,
             input TEST_DATA13_data_wen,
             input TEST_DATA13_data_in,
             output TEST_DATA14_data_out,
             output TEST_DATA14_data_rd,
             output TEST_DATA14_data_wr,
             input TEST_DATA14_data_wen,
             input TEST_DATA14_data_in,
             output TEST_DATA15_data_out,
             output TEST_DATA15_data_rd,
             output TEST_DATA15_data_wr,
             input TEST_DATA15_data_wen,
             input TEST_DATA15_data_in,
             input status_a_in,
             output status_a_rd,
             input status_b_in,
             output status_b_rd,
             input data_err_a_in,
             output data_err_a_rd,
             input addr_err_a_in,
             output addr_err_a_rd,
             input data_err_b_in,
             output data_err_b_rd,
             input addr_err_b_in,
             output addr_err_b_rd);


modport usr(input port_sel_out,
            input port_sel_rd,
            input port_sel_wr,
            output port_sel_wen,
            output port_sel_in,
            input mode_sel_out,
            input mode_sel_rd,
            input mode_sel_wr,
            output mode_sel_wen,
            output mode_sel_in,
            input head_err_cnt_out,
            input head_err_cnt_rd,
            input head_err_cnt_wr,
            output head_err_cnt_in,
            output head_err_cnt_wen,
            input tail_err_cnt_out,
            input tail_err_cnt_rd,
            input tail_err_cnt_wr,
            output tail_err_cnt_in,
            output tail_err_cnt_wen,
            input short_pkt_cnt_out,
            input short_pkt_cnt_rd,
            input short_pkt_cnt_wr,
            output short_pkt_cnt_in,
            output short_pkt_cnt_wen,
            input long_pkt_cnt_out,
            input long_pkt_cnt_rd,
            input long_pkt_cnt_wr,
            output long_pkt_cnt_in,
            output long_pkt_cnt_wen,
            input ok_pkt_cnt_out,
            input ok_pkt_cnt_rd,
            input ok_pkt_cnt_wr,
            output ok_pkt_cnt_in,
            output ok_pkt_cnt_wen,
            input TEST_DATA0_data_out,
            input TEST_DATA0_data_rd,
            input TEST_DATA0_data_wr,
            output TEST_DATA0_data_wen,
            output TEST_DATA0_data_in,
            input TEST_DATA1_data_out,
            input TEST_DATA1_data_rd,
            input TEST_DATA1_data_wr,
            output TEST_DATA1_data_wen,
            output TEST_DATA1_data_in,
            input TEST_DATA2_data_out,
            input TEST_DATA2_data_rd,
            input TEST_DATA2_data_wr,
            output TEST_DATA2_data_wen,
            output TEST_DATA2_data_in,
            input TEST_DATA3_data_out,
            input TEST_DATA3_data_rd,
            input TEST_DATA3_data_wr,
            output TEST_DATA3_data_wen,
            output TEST_DATA3_data_in,
            input TEST_DATA4_data_out,
            input TEST_DATA4_data_rd,
            input TEST_DATA4_data_wr,
            output TEST_DATA4_data_wen,
            output TEST_DATA4_data_in,
            input TEST_DATA5_data_out,
            input TEST_DATA5_data_rd,
            input TEST_DATA5_data_wr,
            output TEST_DATA5_data_wen,
            output TEST_DATA5_data_in,
            input TEST_DATA6_data_out,
            input TEST_DATA6_data_rd,
            input TEST_DATA6_data_wr,
            output TEST_DATA6_data_wen,
            output TEST_DATA6_data_in,
            input TEST_DATA7_data_out,
            input TEST_DATA7_data_rd,
            input TEST_DATA7_data_wr,
            output TEST_DATA7_data_wen,
            output TEST_DATA7_data_in,
            input TEST_DATA8_data_out,
            input TEST_DATA8_data_rd,
            input TEST_DATA8_data_wr,
            output TEST_DATA8_data_wen,
            output TEST_DATA8_data_in,
            input TEST_DATA9_data_out,
            input TEST_DATA9_data_rd,
            input TEST_DATA9_data_wr,
            output TEST_DATA9_data_wen,
            output TEST_DATA9_data_in,
            input TEST_DATA10_data_out,
            input TEST_DATA10_data_rd,
            input TEST_DATA10_data_wr,
            output TEST_DATA10_data_wen,
            output TEST_DATA10_data_in,
            input TEST_DATA11_data_out,
            input TEST_DATA11_data_rd,
            input TEST_DATA11_data_wr,
            output TEST_DATA11_data_wen,
            output TEST_DATA11_data_in,
            input TEST_DATA12_data_out,
            input TEST_DATA12_data_rd,
            input TEST_DATA12_data_wr,
            output TEST_DATA12_data_wen,
            output TEST_DATA12_data_in,
            input TEST_DATA13_data_out,
            input TEST_DATA13_data_rd,
            input TEST_DATA13_data_wr,
            output TEST_DATA13_data_wen,
            output TEST_DATA13_data_in,
            input TEST_DATA14_data_out,
            input TEST_DATA14_data_rd,
            input TEST_DATA14_data_wr,
            output TEST_DATA14_data_wen,
            output TEST_DATA14_data_in,
            input TEST_DATA15_data_out,
            input TEST_DATA15_data_rd,
            input TEST_DATA15_data_wr,
            output TEST_DATA15_data_wen,
            output TEST_DATA15_data_in,
            output status_a_in,
            input status_a_rd,
            output status_b_in,
            input status_b_rd,
            output data_err_a_in,
            input data_err_a_rd,
            output addr_err_a_in,
            input addr_err_a_rd,
            output data_err_b_in,
            input data_err_b_rd,
            output addr_err_b_in,
            input addr_err_b_rd);

endinterface



module ral_blk_PPU_REG_ppu_reg_rtl(vmm_ral_host_itf.slave hst,
                                   ral_blk_PPU_REG_ppu_reg_itf.regs usr);
reg hst_ack;
assign hst.ack = hst_ack;
reg [3:0] PORT_SEL_sel;
reg [3:0] MODE_SEL_sel;
reg [3:0] SPT_HEAD_ERR_CNT_sel;
reg [3:0] SPT_TAIL_ERR_CNT_sel;
reg [3:0] SPT_SHT_PKT_CNT_sel;
reg [3:0] SPT_LNG_PKT_CNT_sel;
reg [3:0] SPT_OK_PKT_CNT_sel;
reg [3:0] TEST_DATA0_sel;
reg [3:0] TEST_DATA1_sel;
reg [3:0] TEST_DATA2_sel;
reg [3:0] TEST_DATA3_sel;
reg [3:0] TEST_DATA4_sel;
reg [3:0] TEST_DATA5_sel;
reg [3:0] TEST_DATA6_sel;
reg [3:0] TEST_DATA7_sel;
reg [3:0] TEST_DATA8_sel;
reg [3:0] TEST_DATA9_sel;
reg [3:0] TEST_DATA10_sel;
reg [3:0] TEST_DATA11_sel;
reg [3:0] TEST_DATA12_sel;
reg [3:0] TEST_DATA13_sel;
reg [3:0] TEST_DATA14_sel;
reg [3:0] TEST_DATA15_sel;
reg [3:0] TEST_STATUS_sel;
reg [3:0] TEST_ALARM_sel;

always @(*)
   begin
      PORT_SEL_sel = 'b0;
      MODE_SEL_sel = 'b0;
      SPT_HEAD_ERR_CNT_sel = 'b0;
      SPT_TAIL_ERR_CNT_sel = 'b0;
      SPT_SHT_PKT_CNT_sel = 'b0;
      SPT_LNG_PKT_CNT_sel = 'b0;
      SPT_OK_PKT_CNT_sel = 'b0;
      TEST_DATA0_sel = 'b0;
      TEST_DATA1_sel = 'b0;
      TEST_DATA2_sel = 'b0;
      TEST_DATA3_sel = 'b0;
      TEST_DATA4_sel = 'b0;
      TEST_DATA5_sel = 'b0;
      TEST_DATA6_sel = 'b0;
      TEST_DATA7_sel = 'b0;
      TEST_DATA8_sel = 'b0;
      TEST_DATA9_sel = 'b0;
      TEST_DATA10_sel = 'b0;
      TEST_DATA11_sel = 'b0;
      TEST_DATA12_sel = 'b0;
      TEST_DATA13_sel = 'b0;
      TEST_DATA14_sel = 'b0;
      TEST_DATA15_sel = 'b0;
      TEST_STATUS_sel = 'b0;
      TEST_ALARM_sel = 'b0;

      hst_ack = 0;

      if (hst.adr == 'h4000) begin
         PORT_SEL_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h4004) begin
         MODE_SEL_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h4100) begin
         SPT_HEAD_ERR_CNT_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h4104) begin
         SPT_TAIL_ERR_CNT_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h4108) begin
         SPT_SHT_PKT_CNT_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h410c) begin
         SPT_LNG_PKT_CNT_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h4110) begin
         SPT_OK_PKT_CNT_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8000) begin
         TEST_DATA0_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8004) begin
         TEST_DATA1_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8008) begin
         TEST_DATA2_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h800c) begin
         TEST_DATA3_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8010) begin
         TEST_DATA4_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8014) begin
         TEST_DATA5_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8018) begin
         TEST_DATA6_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h801c) begin
         TEST_DATA7_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8020) begin
         TEST_DATA8_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8024) begin
         TEST_DATA9_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8028) begin
         TEST_DATA10_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h802c) begin
         TEST_DATA11_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8030) begin
         TEST_DATA12_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8034) begin
         TEST_DATA13_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8038) begin
         TEST_DATA14_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h803c) begin
         TEST_DATA15_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8100) begin
         TEST_STATUS_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
      if (hst.adr == 'h8200) begin
         TEST_ALARM_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
   end


wire [31:0] PORT_SEL_out;
ral_reg_PPU_REG_ppu_reg_PORT_SEL_rtl PORT_SEL(hst.clk, hst.rstn,
                                              hst.wdat[31:0], PORT_SEL_out, PORT_SEL_sel, hst.wen,
                                              usr.port_sel_out,
                                              usr.port_sel_rd,
                                              usr.port_sel_wr,
                                              usr.port_sel_wen,
                                              usr.port_sel_in);

wire [31:0] MODE_SEL_out;
ral_reg_PPU_REG_ppu_reg_MODE_SEL_rtl MODE_SEL(hst.clk, hst.rstn,
                                              hst.wdat[31:0], MODE_SEL_out, MODE_SEL_sel, hst.wen,
                                              usr.mode_sel_out,
                                              usr.mode_sel_rd,
                                              usr.mode_sel_wr,
                                              usr.mode_sel_wen,
                                              usr.mode_sel_in);

wire [31:0] SPT_HEAD_ERR_CNT_out;
ral_reg_PPU_REG_ppu_reg_SPT_HEAD_ERR_CNT_rtl SPT_HEAD_ERR_CNT(hst.clk, hst.rstn,
                                                              hst.wdat[31:0], SPT_HEAD_ERR_CNT_out, SPT_HEAD_ERR_CNT_sel, hst.wen,
                                                              usr.head_err_cnt_out,
                                                              usr.head_err_cnt_rd,
                                                              usr.head_err_cnt_wr,
                                                              usr.head_err_cnt_in,
                                                              usr.head_err_cnt_wen);

wire [31:0] SPT_TAIL_ERR_CNT_out;
ral_reg_PPU_REG_ppu_reg_SPT_TAIL_ERR_CNT_rtl SPT_TAIL_ERR_CNT(hst.clk, hst.rstn,
                                                              hst.wdat[31:0], SPT_TAIL_ERR_CNT_out, SPT_TAIL_ERR_CNT_sel, hst.wen,
                                                              usr.tail_err_cnt_out,
                                                              usr.tail_err_cnt_rd,
                                                              usr.tail_err_cnt_wr,
                                                              usr.tail_err_cnt_in,
                                                              usr.tail_err_cnt_wen);

wire [31:0] SPT_SHT_PKT_CNT_out;
ral_reg_PPU_REG_ppu_reg_SPT_SHT_PKT_CNT_rtl SPT_SHT_PKT_CNT(hst.clk, hst.rstn,
                                                            hst.wdat[31:0], SPT_SHT_PKT_CNT_out, SPT_SHT_PKT_CNT_sel, hst.wen,
                                                            usr.short_pkt_cnt_out,
                                                            usr.short_pkt_cnt_rd,
                                                            usr.short_pkt_cnt_wr,
                                                            usr.short_pkt_cnt_in,
                                                            usr.short_pkt_cnt_wen);

wire [31:0] SPT_LNG_PKT_CNT_out;
ral_reg_PPU_REG_ppu_reg_SPT_LNG_PKT_CNT_rtl SPT_LNG_PKT_CNT(hst.clk, hst.rstn,
                                                            hst.wdat[31:0], SPT_LNG_PKT_CNT_out, SPT_LNG_PKT_CNT_sel, hst.wen,
                                                            usr.long_pkt_cnt_out,
                                                            usr.long_pkt_cnt_rd,
                                                            usr.long_pkt_cnt_wr,
                                                            usr.long_pkt_cnt_in,
                                                            usr.long_pkt_cnt_wen);

wire [31:0] SPT_OK_PKT_CNT_out;
ral_reg_PPU_REG_ppu_reg_SPT_OK_PKT_CNT_rtl SPT_OK_PKT_CNT(hst.clk, hst.rstn,
                                                          hst.wdat[31:0], SPT_OK_PKT_CNT_out, SPT_OK_PKT_CNT_sel, hst.wen,
                                                          usr.ok_pkt_cnt_out,
                                                          usr.ok_pkt_cnt_rd,
                                                          usr.ok_pkt_cnt_wr,
                                                          usr.ok_pkt_cnt_in,
                                                          usr.ok_pkt_cnt_wen);

wire [31:0] TEST_DATA0_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA0_rtl TEST_DATA0(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA0_out, TEST_DATA0_sel, hst.wen,
                                                  usr.TEST_DATA0_data_out,
                                                  usr.TEST_DATA0_data_rd,
                                                  usr.TEST_DATA0_data_wr,
                                                  usr.TEST_DATA0_data_wen,
                                                  usr.TEST_DATA0_data_in);

wire [31:0] TEST_DATA1_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA1_rtl TEST_DATA1(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA1_out, TEST_DATA1_sel, hst.wen,
                                                  usr.TEST_DATA1_data_out,
                                                  usr.TEST_DATA1_data_rd,
                                                  usr.TEST_DATA1_data_wr,
                                                  usr.TEST_DATA1_data_wen,
                                                  usr.TEST_DATA1_data_in);

wire [31:0] TEST_DATA2_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA2_rtl TEST_DATA2(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA2_out, TEST_DATA2_sel, hst.wen,
                                                  usr.TEST_DATA2_data_out,
                                                  usr.TEST_DATA2_data_rd,
                                                  usr.TEST_DATA2_data_wr,
                                                  usr.TEST_DATA2_data_wen,
                                                  usr.TEST_DATA2_data_in);

wire [31:0] TEST_DATA3_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA3_rtl TEST_DATA3(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA3_out, TEST_DATA3_sel, hst.wen,
                                                  usr.TEST_DATA3_data_out,
                                                  usr.TEST_DATA3_data_rd,
                                                  usr.TEST_DATA3_data_wr,
                                                  usr.TEST_DATA3_data_wen,
                                                  usr.TEST_DATA3_data_in);

wire [31:0] TEST_DATA4_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA4_rtl TEST_DATA4(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA4_out, TEST_DATA4_sel, hst.wen,
                                                  usr.TEST_DATA4_data_out,
                                                  usr.TEST_DATA4_data_rd,
                                                  usr.TEST_DATA4_data_wr,
                                                  usr.TEST_DATA4_data_wen,
                                                  usr.TEST_DATA4_data_in);

wire [31:0] TEST_DATA5_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA5_rtl TEST_DATA5(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA5_out, TEST_DATA5_sel, hst.wen,
                                                  usr.TEST_DATA5_data_out,
                                                  usr.TEST_DATA5_data_rd,
                                                  usr.TEST_DATA5_data_wr,
                                                  usr.TEST_DATA5_data_wen,
                                                  usr.TEST_DATA5_data_in);

wire [31:0] TEST_DATA6_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA6_rtl TEST_DATA6(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA6_out, TEST_DATA6_sel, hst.wen,
                                                  usr.TEST_DATA6_data_out,
                                                  usr.TEST_DATA6_data_rd,
                                                  usr.TEST_DATA6_data_wr,
                                                  usr.TEST_DATA6_data_wen,
                                                  usr.TEST_DATA6_data_in);

wire [31:0] TEST_DATA7_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA7_rtl TEST_DATA7(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA7_out, TEST_DATA7_sel, hst.wen,
                                                  usr.TEST_DATA7_data_out,
                                                  usr.TEST_DATA7_data_rd,
                                                  usr.TEST_DATA7_data_wr,
                                                  usr.TEST_DATA7_data_wen,
                                                  usr.TEST_DATA7_data_in);

wire [31:0] TEST_DATA8_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA8_rtl TEST_DATA8(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA8_out, TEST_DATA8_sel, hst.wen,
                                                  usr.TEST_DATA8_data_out,
                                                  usr.TEST_DATA8_data_rd,
                                                  usr.TEST_DATA8_data_wr,
                                                  usr.TEST_DATA8_data_wen,
                                                  usr.TEST_DATA8_data_in);

wire [31:0] TEST_DATA9_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA9_rtl TEST_DATA9(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_DATA9_out, TEST_DATA9_sel, hst.wen,
                                                  usr.TEST_DATA9_data_out,
                                                  usr.TEST_DATA9_data_rd,
                                                  usr.TEST_DATA9_data_wr,
                                                  usr.TEST_DATA9_data_wen,
                                                  usr.TEST_DATA9_data_in);

wire [31:0] TEST_DATA10_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA10_rtl TEST_DATA10(hst.clk, hst.rstn,
                                                    hst.wdat[31:0], TEST_DATA10_out, TEST_DATA10_sel, hst.wen,
                                                    usr.TEST_DATA10_data_out,
                                                    usr.TEST_DATA10_data_rd,
                                                    usr.TEST_DATA10_data_wr,
                                                    usr.TEST_DATA10_data_wen,
                                                    usr.TEST_DATA10_data_in);

wire [31:0] TEST_DATA11_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA11_rtl TEST_DATA11(hst.clk, hst.rstn,
                                                    hst.wdat[31:0], TEST_DATA11_out, TEST_DATA11_sel, hst.wen,
                                                    usr.TEST_DATA11_data_out,
                                                    usr.TEST_DATA11_data_rd,
                                                    usr.TEST_DATA11_data_wr,
                                                    usr.TEST_DATA11_data_wen,
                                                    usr.TEST_DATA11_data_in);

wire [31:0] TEST_DATA12_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA12_rtl TEST_DATA12(hst.clk, hst.rstn,
                                                    hst.wdat[31:0], TEST_DATA12_out, TEST_DATA12_sel, hst.wen,
                                                    usr.TEST_DATA12_data_out,
                                                    usr.TEST_DATA12_data_rd,
                                                    usr.TEST_DATA12_data_wr,
                                                    usr.TEST_DATA12_data_wen,
                                                    usr.TEST_DATA12_data_in);

wire [31:0] TEST_DATA13_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA13_rtl TEST_DATA13(hst.clk, hst.rstn,
                                                    hst.wdat[31:0], TEST_DATA13_out, TEST_DATA13_sel, hst.wen,
                                                    usr.TEST_DATA13_data_out,
                                                    usr.TEST_DATA13_data_rd,
                                                    usr.TEST_DATA13_data_wr,
                                                    usr.TEST_DATA13_data_wen,
                                                    usr.TEST_DATA13_data_in);

wire [31:0] TEST_DATA14_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA14_rtl TEST_DATA14(hst.clk, hst.rstn,
                                                    hst.wdat[31:0], TEST_DATA14_out, TEST_DATA14_sel, hst.wen,
                                                    usr.TEST_DATA14_data_out,
                                                    usr.TEST_DATA14_data_rd,
                                                    usr.TEST_DATA14_data_wr,
                                                    usr.TEST_DATA14_data_wen,
                                                    usr.TEST_DATA14_data_in);

wire [31:0] TEST_DATA15_out;
ral_reg_PPU_REG_ppu_reg_TEST_DATA15_rtl TEST_DATA15(hst.clk, hst.rstn,
                                                    hst.wdat[31:0], TEST_DATA15_out, TEST_DATA15_sel, hst.wen,
                                                    usr.TEST_DATA15_data_out,
                                                    usr.TEST_DATA15_data_rd,
                                                    usr.TEST_DATA15_data_wr,
                                                    usr.TEST_DATA15_data_wen,
                                                    usr.TEST_DATA15_data_in);

wire [31:0] TEST_STATUS_out;
ral_reg_PPU_REG_ppu_reg_TEST_STATUS_rtl TEST_STATUS(hst.clk, hst.rstn,
                                                    hst.wdat[31:0], TEST_STATUS_out, TEST_STATUS_sel, hst.wen,
                                                    usr.status_a_in,
                                                    usr.status_a_rd,
                                                    usr.status_b_in,
                                                    usr.status_b_rd);

wire [31:0] TEST_ALARM_out;
ral_reg_PPU_REG_ppu_reg_TEST_ALARM_rtl TEST_ALARM(hst.clk, hst.rstn,
                                                  hst.wdat[31:0], TEST_ALARM_out, TEST_ALARM_sel, hst.wen,
                                                  usr.data_err_a_in,
                                                  usr.data_err_a_rd,
                                                  usr.addr_err_a_in,
                                                  usr.addr_err_a_rd,
                                                  usr.data_err_b_in,
                                                  usr.data_err_b_rd,
                                                  usr.addr_err_b_in,
                                                  usr.addr_err_b_rd);


reg [31:0] _rdat;
always @(*)
   begin
      _rdat = 32'b0;
      unique casez ({|PORT_SEL_sel[3:0],
                    |MODE_SEL_sel[3:0], |SPT_HEAD_ERR_CNT_sel[3:0],
                    |SPT_TAIL_ERR_CNT_sel[3:0], |SPT_SHT_PKT_CNT_sel[3:0],
                    |SPT_LNG_PKT_CNT_sel[3:0], |SPT_OK_PKT_CNT_sel[3:0],
                    |TEST_DATA0_sel[3:0], |TEST_DATA1_sel[3:0],
                    |TEST_DATA2_sel[3:0], |TEST_DATA3_sel[3:0],
                    |TEST_DATA4_sel[3:0], |TEST_DATA5_sel[3:0],
                    |TEST_DATA6_sel[3:0], |TEST_DATA7_sel[3:0],
                    |TEST_DATA8_sel[3:0], |TEST_DATA9_sel[3:0],
                    |TEST_DATA10_sel[3:0], |TEST_DATA11_sel[3:0],
                    |TEST_DATA12_sel[3:0], |TEST_DATA13_sel[3:0],
                    |TEST_DATA14_sel[3:0], |TEST_DATA15_sel[3:0],
                    |TEST_STATUS_sel[3:0], |TEST_ALARM_sel[3:0]})
         25'b1????????????????????????: _rdat = PORT_SEL_out;
         25'b?1???????????????????????: _rdat = MODE_SEL_out;
         25'b??1??????????????????????: _rdat = SPT_HEAD_ERR_CNT_out;
         25'b???1?????????????????????: _rdat = SPT_TAIL_ERR_CNT_out;
         25'b????1????????????????????: _rdat = SPT_SHT_PKT_CNT_out;
         25'b?????1???????????????????: _rdat = SPT_LNG_PKT_CNT_out;
         25'b??????1??????????????????: _rdat = SPT_OK_PKT_CNT_out;
         25'b???????1?????????????????: _rdat = TEST_DATA0_out;
         25'b????????1????????????????: _rdat = TEST_DATA1_out;
         25'b?????????1???????????????: _rdat = TEST_DATA2_out;
         25'b??????????1??????????????: _rdat = TEST_DATA3_out;
         25'b???????????1?????????????: _rdat = TEST_DATA4_out;
         25'b????????????1????????????: _rdat = TEST_DATA5_out;
         25'b?????????????1???????????: _rdat = TEST_DATA6_out;
         25'b??????????????1??????????: _rdat = TEST_DATA7_out;
         25'b???????????????1?????????: _rdat = TEST_DATA8_out;
         25'b????????????????1????????: _rdat = TEST_DATA9_out;
         25'b?????????????????1???????: _rdat = TEST_DATA10_out;
         25'b??????????????????1??????: _rdat = TEST_DATA11_out;
         25'b???????????????????1?????: _rdat = TEST_DATA12_out;
         25'b????????????????????1????: _rdat = TEST_DATA13_out;
         25'b?????????????????????1???: _rdat = TEST_DATA14_out;
         25'b??????????????????????1??: _rdat = TEST_DATA15_out;
         25'b???????????????????????1?: _rdat = TEST_STATUS_out;
         25'b????????????????????????1: _rdat = TEST_ALARM_out;
         default: _rdat = 32'b0;
      endcase
   end
assign hst.rdat[31:0] = _rdat;

endmodule
`endif
